Computer systems (and related devices) typically create three-dimensional images using a sequence of stages known as a graphics pipeline. During early pipeline stages, images are modeled using a mosaic-like approach where each image is composed of a collection of individual points, lines and polygons. These points, lines and polygons are known as primitives and a single image may require thousands, or even millions, of primitives. Each primitive is defined in terms of its shape and location as well as other attributes, such as color and texture.
The primitives used in early pipeline stages are transformed, during a rasterization stage, into collections of pixel values. The rasterization stage is often performed by a specialized graphics processor (in low-end systems, rasterization may be performed directly by the host processor) and the resulting pixel values are stored in a device known as a frame buffer. A frame buffer is a memory that includes a series of randomly accessible memory locations. Each memory location in the frame buffer defines a corresponding pixel included in an output device where the image will ultimately be displayed. To define its corresponding pixel, each memory location includes a series of bits. Typically, these bits are divided into separate portions defining red, blue and green intensities. Each memory location may also include depth information to help determine pixel ownership between overlapping primitives.
During the rasterization stage, the graphics processor renders each primitive into the frame buffer. The graphics processor accomplishes this task by determining which frame buffer memory locations are included within the bounds of each primitive. The included memory locations are then initialized to reflect the attributes of the primitive, including color and texture.
The rasterization stage is followed by a display stage where a display controller transforms the pixel values stored in the frame buffer into signals that drive the output device being used. The display controller accomplishes this task by scanning the memory locations included in the frame buffer. The red, blue and green portions of each location are converted into appropriate output signals and sent to the output device.
The throughput of a graphics pipeline is highly dependent on frame buffer performance. This follows because the frame buffer functions as a middleman between the rasterization stage and the display stage. As a result, the frame buffer becomes the focus of repeated memory accesses by both the graphics processor and the display controller. The number of these accesses may be quite large. The frame buffer must be able to sustain a high rate of these accesses if it is to avoid becoming a performance bottleneck.
Frame buffers are typically fabricated using arrays of dynamic random access memory (DRAM) components. Compared to other technologies, such as static random access memories (SRAMs), DRAM components represents a better trade off between performance and cost. At the same time, achieving acceptable frame buffer performance may be far more complicated when DRAM components are used. The complexity involved in DRAM use stems from the addressing scheme used by these components. For this scheme, memory locations are addressed using a combination of a row address and a column address. Row and column addresses are supplied in sequence—row address first, column address second. Depending on the specific type of DRAM components used, this two-step addressing scheme may be too time consuming to sustain the memory access rate required for frame buffer use.
Fortunately, many DRAM components also provide a faster page addressing mode. For this mode, a sequence of column addresses may be supplied to a DRAM component after the row address has been supplied. Accesses within a row require only a single address. The overall effect is that accessing a DRAM component is much faster when a series of accesses is confined to a single row. Accessing a location included in a new row, referred to as a page miss, is much slower.
For this reason, frame buffers are often designed to maximize consecutive accesses within DRAM rows and to minimize page misses. One way in which this is accomplished is to structure the frame buffer so that graphics primitives tend to map to a single DRAM row or a small number of DRAM rows. Memory tiling is an example of this type of frame buffer structuring. In frame buffers that use memory tiling, the memory locations included in a DRAM row map to a rectangular block of pixels. This contrasts with more typical frame buffer construction where DRAM rows map to lines of pixels. Memory tiling takes advantage of the fact that many primitives fit easily into blocks and that few fit easily into lines. In this ways memory tiling reduces page misses by increasing the chances that a given primitive will be included within single DRAM row or a small number of DRAM rows.
Another way to maximize consecutive accesses within DRAM rows and to minimize page misses is to position a cache memory between the graphics processor and the frame buffer. The cache memory collects accesses performed by the graphics processor and forwards them to the cache on a more efficient row-by-row basis.
Memory tiling and cache memories are both effective techniques for improving the performance of DRAM based frame buffers. Unfortunately, the rasterization technique used within most frame buffers does not fully exploit the full potential of memory tiling or cache memories used in combination with memory tiling. This follows because rasterization is typically performed on a line-by-line basis. When used in a tiled frame buffer, line-by-line rasterization effectively ignores the tiled structure of the frame buffer. As a result, a given rasterization may alternately access and re-access a given set of tiles. This results in an increased number of DRAM page misses and decreases the throughput of the frame buffer and graphics pipeline. As a result, there is a need for rasterization methods that more effectively exploit the full potential of memory tiling and cache memories used in combination with memory tiling.